1. Field of the Invention
The present invention relates to a logic circuit which evaluates a delay relationship and a delay time among digital signals.
2. Description of the Related Art
In recent years, an integrated circuit formed over a single crystalline silicon substrate is showing a remarkable progress in its scale and frequency. In such a logic circuit, it is important that variations in delay of clock signals and the like are controlled since frequency characteristics decrease in accordance with more variations, which may cause a malfunction in some cases. Therefore, in the conventional design, an integrated circuit is divided into regions so that the variations in delay are not a problem, and a variation in delay between signals inputted to each region is accurately estimated by simulation.
Further, a technology to form a thin film transistor (hereinafter referred to as a TFT) over a glass substrate is being improved and a technology to form an integrated circuit over a glass substrate is actively developed these years. The TFTs, however, have more variations in characteristics and occupy more area as compared to a transistor formed over a single crystalline silicon substrate. As these characteristics cause to increase the variations in delay among signals, it is a problem of an integrated circuit formed on a glass substrate that it is difficult to improve operation speed and yield. In such an integrated circuit, it is more vital to accurately estimate delay time of a clock signal and the like.